This invention is related to U.S. patent application Ser. No. 08/931,343, entitled xe2x80x9cA Low Noise, High Current-Drive MOSFET Structure for Uniform Poly-Gate Turn-On During an ESD Eventxe2x80x9d, and U.S. patent application Ser. No. 08/931,594, entitled xe2x80x9cA Distributed MOSFET Structure with Enclosed Gate for Improved Transistor Size/Layout Area Ratio and Uniform ESD Triggeringxe2x80x9d, filed on even date herewith for Shi-Tron Lin. The contents of the above-noted applications are incorporated herein by reference.
The present invention relates to a MOSFET structure for use in ESD applications. More specifically, the present invention relates to a multi-gate-finger MOSFET structure which enhances high speed, uniform turn-on during an ESD event.
An NMOSFET is a very effective ESD protection device. In one application, it is used as the pull down transistor of a CMOS buffer to drive an output voltage for an external device. In this type of application, the gate of the NMOSFET is connected to an input drive signal.
In another common NMOSFET application, the gate is electrically connected to ground, and the NMOSFET is used as an ESD protection device for an input pin or a power bus during an ESD event.
The ESD protective action of an NMOSFET is based on the device""s snap-back mechanism, which enables the NMOSFET to conduct a high level of ESD current between its drain and source. This occurs when a strong electric field across the depletion region in the drain substrate junction becomes high enough to begin avalanche breakdown, which in turn causes impact ionization, resulting in the generation of both minority and majority carriers. The minority carriers flow toward the drain contact, and the majority carriers flow toward the substrate/p-well contact, causing a local potential build up across the current path in the p-well substrate. When the local substrate potential is 0.6V higher than an adjacent n+ source potential, the source junction becomes forward biased. The forward biased source junction then injects minority carriers (electrons) into the p-well, and these carriers eventually reach the drain junction to further enhance the impact ionization effect (see xe2x80x9cESD in Silicon Integrated Circuits,xe2x80x9dby A. Amerasekera and C. Duvvury, Chap. 3, Sec. 1., John Wiley and Sons, 1995). Eventually, the NMOSFET reaches a low impedance (snap-back) state, which enables it to conduct a large amount of ESD current.
To enhance the ESD protection capabilities of a MOSFET device, it is desirable to have a rapid turn on with a high degree of uniformity throughout the device. A known technique for accomplishing these objectives utilizes a multi-gate-finger configuration of reduced length poly gate fingers to speed up the gate signal propagation and to increase the effective gate width. However, in a typical multi-gate-finger NMOS structure, as shown in FIGS. 2a and 2b, not all the poly gate fingers may turn on during an ESD event. That is, when the first few gate fingers reach their snap-back low impedance mode, the drain terminal to source terminal voltage is reduced to a value, called the snap-back voltage, which is less than the trigger voltage of the NMOS device. This has the effect of preventing the remaining gate fingers from being turned on. As a result, only a partial number of the gate fingers are available to absorb the ESD energy. Therefore, the ESD protection provided by the NMOSFET is significantly reduced.
When a MOSFET gate finger is triggered during an ESD event, the entire finger turns on. This is due to the cascading effect of the previously described impact ionization and snapback process along the entire gate finger. It is clearly desirable to turn on all of the gate fingers of a multi-gate-finger MOSFET as simultaneously (uniformly) as possible, for maximum ESD effectiveness.
One prior art technique for improving the uniform turn on of a multi-gate-finger NMOSFET structure uses a gate coupled technique, as shown in FIG. 3, and as described in xe2x80x9cESD in Silicon Integrated Circuits,xe2x80x9d by A. Amerasekera and C. Duvvury, Chap. 4, Sec. 2., John Wiley and Sons, 1995. In this configuration, the drain is connected to either VDD or the buffer output line, and the gate is coupled to the drain via a capacitor C, and is also connected to ground via a resistor R. The coupling capacitor C and the RC time constant of the circuit cause the gate potential to rise to 1 to 2v during the first 5 to 10 ns of an ESD event. The positive gate voltage reduces the triggering threshold of the NMOSFET, thereby enabling a more uniform turn-on of the gate fingers. This method, however, has the disadvantage of requiring additional layout area for the coupling capacitor C and the resistor R. In addition, since the gate is connected to ground through a resistor R, this configuration is not particularly well suited for an output buffer application.
Another type of prior art multi-gate-finger structure, as described in U.S. Pat. No. 4,462,041, by R. Douglas Glenn, uses a serpentine-like gate structure, of the type depicted in FIG. 4, with a metal line routed along the gate in order to make multiple metal-to-poly-gate contacts. Due to the low resistance of the metal line, the effective gate resistance is greatly reduced, thereby increasing the gate signal propagation speed.
With respect to ESD uniform turn on, however, this prior art serpentine gate structure is essentially equivalent to a conventional multi-gate-finger structure (FIG. 2a), since each gate finger extends beyond the diffusion area and into the field oxide region. Therefore, as described above, this configuration does not provide optimum ESD protection because of its non-uniform turn on characteristics, in that only a partial number of gate fingers may turn on during an ESD event.
Accordingly, it is an object of the present invention to overcome the disadvantages of the prior art with respect to MOSFET ESD protection. That is, it is an object of the present invention to retain the high speed characteristics of the multi-gate-finger structure, while at the same time improving the turn on uniformity during an ESD event.
In accordance with an illustrative embodiment of the present invention, a multi-gatefinger MOSFET structure is configured to enhance uniform turn on during an ESD event. This is achieved by positioning the active portion of a serpentine-like poly-gate element, overlying a serpentine-like channel layout, between drain and source regions configured in a comb-shaped structure. Importantly, the channel, active gate portion, drain, and source elements are completely contained within an active diffusion area, such that the and channel-to-source diffusion edges are continuous throughout the length of the active gate portion overlying the channel. This enables a cascading snap-back action to develop very rapidly along the active portion of the gate element during the occurrence of an ESD event, thus enhancing the desired uniform turn on of all the MOSFET devices within the diffusion area.
Importantly, multiple poly-gate extensions are provided for connecting the gate to a common gate signal line. This has the effect of minimizing the gate resistance, and thereby maximizing the speed of the MOSFET device.